1. Field of Invention
The disclosure generally relates to chip package interactions (CPIs) between an integrated circuit (IC) chip, a multilayer electronic device, and a connector footprint interposed between the IC chip and the multilayer electronic device in a chip/device package. More particularly, the disclosure relates to providing an elastic modulus map of the IC chip, based on stacked elastic modulus maps of each back-end-of-line (BEOL) layer of the IC chip, that identifies probable mechanical failure sites during chip-join and cool-down of the chip/device package.
2. Description of Related Art
The semiconductor marketplace continues to demand smaller devices, which require greater connectivity densities for packaging design. The increased functionality of smaller semiconductor devices requires an increased number of signal, power and ground connections, and a corresponding decrease in connection pitch is required to maintain reasonable chip size. The combination of these requirements results in greater complexity of semiconductor packaging design.
Referring to FIG. 1, the packaging design requirement is especially critical in a flip chip package 100, i.e., a “flipped” IC chip 110 connected to a chip carrier 120 by interposed connectors of a connector footprint. The connectors 130 can comprise one of solder bumps and copper (Cu) pillars. The connectors connect various signal, power and ground terminals from a final wiring level of the IC chip 110 to corresponding signal, power and ground terminals on the chip carrier 120 of the flip chip package 100. The flip chip package 100 provides significant numbers of signal, power and ground connections from the flipped IC chip 110 of FIG. 1, through solder bumps or Cu pillars 130 to a chip carrier 120. The solder bumps or Cu pillars 130 are formed on ball limiting metallurgy (BLM) structures 150, which are, in turn, formed on an outer surface of the flipped IC chip 110. During chip-join and cool-down, the solder bumps or Cu pillars 130 form electrical and connections with flip chip (FC) pads 140 formed on a top surface of the chip carrier 120. In turn, the FC pads 140 electrically connect through various pathways of the chip carrier 120 to, for example, a ball grid array, or lands/solder balls that connect to a system board.
FIG. 2 illustrates a cross section of an IC chip 200 that includes metallization scheme levels, 250-230. A connector 270 is formed on BLM structure 265, which penetrates passivation layer 260 of the IC chip 200 to make electrical contact with a metal fill, UB, in a topmost metallization layer or back-end-of-line (BEOL) layer of metallization scheme level, 250. Each BEOL layer can comprise one or more design elements, i.e., areas of any of metal fills, metal lines or metal vias, and areas of a dielectric that separate the design elements. For example, referring to FIG. 2, the BEOL layer containing the metal fill, UB, also contains the coplanar dielectric material, tetraethyl orthosilicate (TEOS), which surrounds the metal fill. Each BEOL layer provides voltage planes and/or ground planes that can form portions of passive electrical devices or can redistribute various voltages and signals. The metal fills, metal lines and metal vias are frequently separated from the surrounding dielectric material by a liner.
Generally, metal vias are made by filling a via-hole in the dielectric material of a metallization layer with a liner material, drilling a hole in the liner material, and filling the hole with metal. The metal of metal via, VB, for example, is prevented from diffusing into the dielectric material of the coplanar BEOL layer by the liner material. The metal via, VB, can contact the metal fill, UB, of an overlying BEOL layer, and a metal fill, UA, of an underlying BEOL layer, to provide an electrical connection between an overlying BEOL layer and an underlying BEOL layer. In general, a metal vias electrically connect the active devices of the silicon layers 210 of the IC chip to the appropriate ground planes, voltage planes, signal traces, or passive devices of the BEOL layers of the metallization scheme levels 230-250 for operation and testing of the IC chip 200.
Additionally, FIG. 2 illustrates that metallization scheme levels 230-250 and their BEOL layers can comprise various dielectric materials, e.g., tetraethyl orthosilicate (TEOS), any of various ultra low k dielectric materials, and any of various SiOC:H dielectric films prepared from octamethylcyclo-tetrasiloxane (OMCTS). Furthermore, the dielectric materials of any of the metallization scheme levels 250-230 can be graded to yield corresponding graded physical properties.
Referring to FIG. 2, the feature size of design elements, e.g., a metal fill, a metal line or a metal via, of the BEOL layers in each of the metallization scheme levels 250-230 decreases from topmost metallization scheme level 250 to bottom most metallization scheme level 230 of the IC chip 200. That is, the height and the lateral extent of the design elements decrease from the topmost metallization scheme level 250 to the bottom most metallization scheme level 230 overlying the IC chip 200.
The mechanical stresses and strains that occur with chip package interactions (CPIs) are complex, depending upon many factors including IC chip design, process variations in IC chip manufacture, design of a multilayer electronic device to which the IC chip is connected, process variations in the multilayer electronic device's manufacture and process variations in bond and assembly of the chip/device package. Many CPIs result from stress/strain caused by a mismatch between the coefficients of thermal expansion (CTE) of the IC chip and the multilayer electronic device, e.g., another IC chip or a chip carrier, during the heating and cooling of the chip/device package to join the IC chip and the multilayer electronic device. Differences in contraction during chip-join and cool-down result in shear forces between the IC chip and the multilayer electronic device. These shear forces are usually propagated as stress/strain through the connectors, e.g., solder bumps or Cu pillars, to an interface region of the connector with the IC chip.
One type of chip package interaction (CPI) is a so-called “white bump”, i.e., a white area on a photographically processed acoustic image, used for testing, that is coextensive with a solder bump. Each white bump corresponds to the location of a material fracture, i.e., a test failure, in the interface region between the solder bump and the IC chip. Frequently, the white bump resembles a divot formed beneath the solder bump in the BEOL layers of the IC chip. White bumps typically occur during chip-join and cool-down, or during subsequent handling of the chip/device package before an underfill is introduced between the IC chip and the multilayer electronic device to more uniformly distribute stresses across the IC chip/multilayer electronic device interface.
White bumps are more likely to occur at sites associated with a greater shear force and/or a greater stiffness of materials. Mechanical analysis indicates that the shear forces propagated by a connector on the IC chip are proportional to a radial distance from a central neutral point on the IC chip, i.e., a point that does not move with either thermal expansion or contraction of the IC chip. The elastic modulus (Young's modulus) or stiffness of areas of the IC chip that underlie the connectors, depend on the stiffness of corresponding areas of each of the underlying BEOL layers comprising the areas of the IC chip. Each BEOL layer, when viewed in a top plan view, can vary in stiffness across its area, depending on the location of design elements, e.g., metal fills, metal lines and metal vias, disposed within each BEOL layer.
There remains a need for a method to identify those design elements of back-end-of-line (BEOL) layers of an IC chip of a chip/device package that may contribute to possible “white bump” failures in the chip/device package, based on elastic modulus mappings of the design elements disposed within each of the BEOL layers of the IC chip, and to modify these design elements to decrease the probability of such “white bump” failures.